This invention relates to a driver circuit for an active matrix liquid crystal display comprising a resistive dividing type digital to analog converter circuit.
A driver circuit for an active matrix liquid crystal display capable of displaying multi-scale gray images or full-color images generally comprises a digital-to-analog converter circuit (DAC) so that analog video signals are outputted. A capacitor based DAC is well known in the art as one type of such a DAC. However, such a capacitor based DAC has a drawback in that a linear output voltage characteristic cannot be obtained easily when such a capacitor based DAC is employed in constructing a driver circuit for a liquid crystal display (LCD). In view of this drawback, a resistive dividing type DAC using resistance elements has also been employed for an LCD driver circuit.
Among such resistive dividing type DACs, some types are constructed utilizing resistance elements and switching elements, both having an individual component form, but many types are constructed within a single crystalline silicon integrated circuit (IC) and formed in a chip form. Such a driver IC has been used for conventional LCD driver circuits. Specifically, in those driver circuits having resistive dividing type DACs, driver ICs are attached onto an array substrate by a tape automated bonding or by directly mounting onto the array substrate.
However, such an LCD driver circuit has drawbacks as described in the following.
(1) A driver IC is essential as a component of an LCD, and therefore the component cost is high.
(2) A step of mounting the driver IC onto an array substrate is inevitably required.
(3) The thickness of an LCD is increased corresponding to the thickness of the driver IC, and in addition, the driver IC requires a large area in the array substrate. These have been the major obstacles in the attempts to reduce the physical sizes and thickness of LCDs.
(4) Furthermore, in conventional driver circuits utilizing a crystalline silicon, a silicon in which an n-type or p-type impurity of approximately 1016/cm3 is doped is typically employed for resistance elements that constitute DACs in the driver circuits. A resistance value of these resistance elements must be controlled with extremely high precision by controlling a concentration of these impurities so as to suppress an output variation among these DAC chips. As a result, in order to produce a chip with an extremely precise resistance value, an ion implantation method should be employed in doping an n-type or p-type impurity in a crystalline silicon. However, by this method, it is extremely difficult to suppress a variation of the resistance value within a predetermined range when a large chip size or a large number of the chip is required, and moreover a throughput until completing the driver circuit is low.
In addition to the above drawbacks, conventional LCD driver circuits have such drawbacks as described below, in view of reducing their power consumption.
A resistive dividing type DAC is a well-known circuit, and while some of the DACs are constructed utilizing the resistance elements and switching elements having an individual component form, many of the DACs commercially available have a chip form incorporated within a single crystalline silicon (c-Si) IC. Recently, there have been developed techniques intended to incorporate an LCD driver circuit including such DACs on a glass substrate by forming thin-film transistors (herein after referred as xe2x80x98TFTsxe2x80x99) utilizing poly-silicon (p-Si). However, because p-Si TFTs are inferior to c-Si transistors"" in their performance and thereby in the power efficiency in the circuits, the effective reduction in power consumption has been difficult for such an LCD driver circuit incorporated on the grass substrate, although such a circuit has certain advantages such as low cost and small sizes owing to the fact that they are capable of eliminating driver ICs. In conventional LCD driver circuits, a waste of power consumption is noted particularly during a writing period for source lines and pixel electrodes. The discussion will now focus on this account. Generally speaking, a large amount of capacitive load is connected to a source line because a certain capacitance is generated in each intersection of a source line and gate line, or in each gap between a source line and counter electrode. Therefore, when a driving voltage is outputted from a driver circuit to a source line, a potential of the source line does not reach a required voltage for driving liquid crystals immediately after the driving voltage is outputted, and a certain amount of time is required until a desired voltage is obtained. After this amount of time, i.e., a writing period to a source line elapses, a gate scanning pulse is outputted to a pixel transistor, and thereby a potential of a pixel electrode reaches a desired voltage. Or, a gate scanning pulse is outputted almost simultaneously with an output of a driving voltage, and a potential of a pixel electrode reaches a desired voltage corresponding to the change of a potential of a source line. A writing to a pixel electrode is thus completed according to either of the above described manners. Therefore, there is essentially no need to continue applying a predetermined driving voltage to a source line. Nevertheless, in conventional driving methods, such a writing period to a source line or a pixel electrode has been made equivalent to one horizontal synchronizing period. This is because the writing to a source line or a pixel electrode has been controlled by a horizontal synchronizing signal. As a result, in prior arts, the driver circuit continues a normal operation for applying a driving voltage even during the period in which there is no need to keep applying a predetermined driving voltage to a source line. This has been a major drawback from the viewpoint of reduction in power consumption.
In view of the above-described disadvantages in prior arts, it is therefore an object of the present invention to provide a driver circuit for an active matrix liquid crystal display in which, by eliminating a driver IC from a component of an LCD, the component cost is reduced, the manufacturing steps are simplified, and moreover the reduction of sizes and thickness is achieved.
It is another object of the present invention to provide a driver circuit for an active matrix liquid crystal display in which the reduction of power consumption is achieved by reducing a current consumption of the digital-analog converter circuits therein during a period excluding a normal operation period.
In accordance with the first aspect of the invention, there is provided a driver circuit for an active matrix liquid crystal display formed on an array substrate of the liquid crystal display comprising:
a resistive dividing type digital-to-analog converter circuit (DAC), comprising a plurality of resistance elements and a plurality of switches related to the resistance elements;
the driver circuit constructed so that an output signal from the DAC is outputted as a driving voltage for a liquid crystal display portion of the liquid crystal display via a current amplifier element having an impedance conversion function wherein a voltage amplification ratio of the current amplifier element is 1;
the driver circuit characterized in that the resistance elements are composed of an impurity-containing semiconductor layer formed on the array substrate.
According to the above-mentioned construction, it is made possible to reduce the component cost of an LCD since the driver circuit is formed on the array substrate without using driver ICs as a component for the LCD. Moreover, it is also made possible to reduce the manufacturing cost since the step of mounting the driver ICs onto the substrate is made unnecessary. In addition, the reduction in the thickness and sizes of an LCD can be achieved easily. In particular, the above-mentioned semiconductor layer is formed simultaneously with a step of forming pixel transistors without independently necessitating an step of forming the above-mentioned semiconductor layer, and therefore it is possible to substantially reduce the manufacturing cost.
Furthermore, according to the above construction, it is made possible to produce resistance elements for a driver circuit having a large circuit area without taking into account a joint areas between each chip since the resistance elements are integrally formed on the array substrate. Generally, a mass non-separated type ion shower method, which has a large throughput, is employed as a method for doping an n-type or p-type impurity over a large area. When this method is employed, a variation of resistance values in the entire glass substrate becomes relatively large, and an output variation in the entire glass substrate becomes approximately 20 mV or higher, but an output variation between the channels next to each other is at most within several mV. It is therefore possible to set a large process margin since there are no joint areas between each chip, as seen in prior arts. The output variation in the entire array is approximately 0.1 V, but this causes no problem since, if converted into a luminance variation in the liquid crystal panel, it falls within the range of 10%.
In addition, since the electric current is amplified by a current amplifier element, an output from the DAC circuit can be made substantially smaller in comparison with a output current necessary to charge a capacitive load of a source line. Therefore, the freedom in designing a circuit increases and the reduction in the display size and manufacturing cost is easily achieved.
For the current amplifier element, a voltage follower type op-amp, a source follower type thin film transistor (TFT), and the like may be employed.
In accordance with the second aspect of the invention, there is provided a driver circuit for an active matrix liquid crystal display formed on an array substrate of the liquid crystal display comprising:
a resistive dividing type DAC, comprising a plurality of resistance elements and a plurality of switches related to the resistance elements;
the driver circuit constructed so that an output signal from each of the DACs is directly outputted as a driving voltage for a liquid crystal display portion of the liquid crystal display;
the driver circuit characterized in that the resistance elements are composed of an impurity-containing semiconductor layer formed on the array substrate.
According to the above construction, the display size and manufacturing cost can be further reduced by making the circuit scale smaller, although the voltage required for driving the LCD portion has to be generated by the DAC circuit alone. In addition, an output voltage characteristic with high precision and small variation can be easily obtained since the voltage from the DAC is directly outputted as a driving voltage for the LCD portion.
Furthermore, according to the above construction in which the signal amplifier element is eliminated, when compared with, for example, the construction with the amplifier element formed on the array substrate among the ones employing the amplifier element, the entire circuit area can be made smaller corresponding to the circuit area allotted for the signal amplifier element, and the power consumption can be also reduced corresponding to the power to be consumed by the amplifier element. Likewise, when compared with the construction with an amplifier element mounted onto array substrate, for example, the cost reduction can be achieved since the amplifier element is eliminated from the components of an LCD, and the step of mounting the amplifier element is also eliminated.
In accordance with the third aspect of the invention, there is provided a driver circuit for an active matrix liquid crystal display comprising:
a resistive dividing type DAC, comprising a plurality of resistance elements and a plurality of switches related to the resistance elements;
the driver circuit constructed so that an output signal from the DAC is outputted as a driving voltage for a liquid crystal display portion of the liquid crystal display via a current amplifier element having an impedance conversion function wherein a voltage amplification ratio of the current amplifier element is 1, the current amplifier element being mounted on the array substrate and a remaining portion of the driver circuit excluding the current amplifier element being formed on the array substrate;
the driver circuit characterized in that the resistance elements are composed of an impurity-containing semiconductor layer formed on the array substrate.
According to the above construction, the manufacturing steps are slightly increased since a step of mounting an amplifier element becomes necessary. The effect of the size and thickness reduction of the LCD also becomes slightly small because of the amplifier element incorporated into an IC chip form. However, in the case of forming the amplifier element on the array substrate, unlike the case of forming switching transistors, it is necessary that the formed transistor be capable of achieving an accurate amplification ratio, and therefore, the manufacturing is rendered very difficult particularly when a non-single crystalline material is utilized. Hence, the construction where an IC chip-formed individual component is employed only for the current amplifier element has an advantage in that the manufacturing is made easier than the construction where the amplifier element is formed on the array substrate.
In accordance with the fourth aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, wherein the semiconductor layer is composed of a non-single crystalline material including silicon and germanium, and contains an impurity which acts as a donor or an acceptor.
According to the above construction, the same effect as in the first aspect of the invention can be attained.
In accordance with the fifth aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, wherein the semiconductor layer is a non-single crystalline silicon layer and is at least one layer of an n-type layer and a p-type layer.
According to the above construction, the same effect as in the first aspect of the invention can be attained.
In accordance with the sixth aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, wherein the DAC is an R-b 2R ladder type DAC.
According to the above construction employing an R-2R ladder type DAC, it is made possible to obtain a linear output voltage characteristic. Moreover, an adverse effect on an output voltage characteristic by a variation of resistance values is rendered small since the DAC is constructed by two types of resistance elements each having a different resistance value. In addition, the total area occupied by the resistance elements in the DAC is made remarkably smaller in comparison with the case where the same output voltage characteristic is realized by utilizing a DAC other than an R-2R ladder type construction.
The reason is as follows. When an R-2R ladder type DAC for four-bit digital input signal is employed, assuming a reference resistance value is r1, the resistance value of all the resistance elements used (note that this means a resistance value converted into a circuit occupying area of resistance elements, not a composite resistance value) results in 13xc3x97r1. Now, assume that a linear output voltage characteristic as in the above construction is realized by utilizing a so-called weighted resistance type DAC. An example of the weighted resistance value type DAC can be realized by the construction as follows. The DAC has two types of power supplies (which correspond to VH and VL in FIG. 2) and a certain number of series circuit connected in parallel. Each of the series circuits has a switching element for alternatively selecting one of the power supplies, and a resistance element with one end connected to the switching element and the other end connected to the output terminal. The number of the series circuit corresponds with the bit number of digital input signal. Each switching state of the switching elements is controlled in response to the digital input signal so as to select one of the power supplies. In this example, a resistance ratio of each resistance element against the reference resistance value (the resistance value of the resistance element responsive to the least significant bit) is set at 1:2nxe2x88x921 (xe2x80x98nxe2x80x99 is the bit number of the digital input signal).
According to this example, in the case of 4-bit digital input signal, if a reference resistance value is r1, the resistance values of the rest of the three resistance elements are 2xc3x97r1, 4xc3x97r1, and 8xc3x97r1 respectively, and the resistance value of all the resistance elements used accordingly results in 15xc3x97r1. On the other hand, in the case of the construction according to the sixth aspect of the invention, the resistance value of all the resistance elements used results in 13xc3x97r1, as described above. Hence, when it is assumed that each of the resistance elements is formed by a non-single crystalline semiconductor layer having an identical sheet resistance, the total area occupied by the resistance elements in the weighted resistance type DAC requires 15/13 times in comparison with the construction according to the sixth aspect of the invention. As the bit number of the digital input signal increases further, the weighted resistance type DAC correspondingly requires a larger total area occupied by the resistance elements than that of the construction according to the sixth aspect of the invention. It is apparent from the above example that the construction according to the sixth aspect of the invention can achieve remarkable reduction of the total area occupied by the resistance element in the DAC.
In accordance with the seventh aspect of the invention, there is provided a driver circuit as in the fourth aspect of the invention, wherein the DAC is an R-2R ladder type DAC.
According to the above construction, the same effect as in the sixth aspect of the invention can be attained.
In accordance with the eighth aspect of the invention, there is provided a driver circuit as in the fifth aspect of the invention, wherein the DAC is an R-2R ladder type DAC.
According to the above construction, the same effect as in the sixth aspect of the invention can be attained.
In accordance with the ninth aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, wherein the DAC is a voltage potentiometer type DAC.
According to the above construction employing a voltage potentiometer type DAC, the output voltage results in the voltage weighted corresponding to the ratio of the resistance values of the resistance elements connected in series. Therefore, the output voltage characteristic can be easily made into the one with a desired curve, not just into a linear characteristic, by appropriately setting the resistance values of the resistance elements. Moreover, if the electric current flowing via the switching elements is small, the current dividing or voltage drop caused by the switching elements is avoided and the output voltage is determined only by the voltage dividing by the resistance elements. Therefore, the circuit can be designed without worrying about ON resistance of the switching elements.
In accordance with the 10th aspect of the invention, there is provided a driver circuit as in the fourth aspect of the invention, wherein the DAC is a voltage potentiometer type DAC.
According to the above construction, the same effect as in the ninth aspect of the invention can be attained.
In accordance with the 11th aspect of the invention, there is provided a driver circuit as in the fifth aspect of the invention, wherein the DAC is a voltage potentiometer type DAC.
According to the above construction, the same effect as in the ninth aspect of the invention can be attained.
In accordance with the 12th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, wherein the DAC comprises:
a first DAC section which operates in response to one of more significant bit data and lesser significant bit data of digital video input data; and
a second DAC section which uses an output voltage as a reference voltage and operates in response to the other one of more significant bit data and lesser significant bit data of digital video input data; and
wherein one of the DAC sections is an R-2R ladder type DAC, and the other one of the DAC sections is a voltage potentiometer type DAC.
According to the above construction, both types of the DACs, an R-2R ladder type DAC and a voltage potentiometer type DAC, are employed for the DACs incorporated in the driver circuit, and thereby it is made possible to obtain a driver circuit having both of the advantages intrinsic to each type of the DACs.
In accordance with the 13th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC is composed of a voltage potentiometer type DAC comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is connected to a high voltage power supply terminal, and the other end is connected to a low voltage power supply terminal;
a first switch connected between the one end of the series circuit and the high voltage power supply terminal or between the other end of the series circuit and the low voltage supply terminal, the first switch to be turned to an ON state during the normal operation period and to be turned to an OFF state during the remaining period in response to the first switching signal; and
a group of second switches wherein a switching state of each of the second switches is controlled in response to a digital video data, and each of the second switches is connected between a connecting point of each of the resistance elements and an output terminal of the DAC.
According to the above construction, the following effects are attained.
During the normal operation period, the first switch is turned to ON state in response to the first switching signal, and the switching states of the second switch group is controlled in response to the digital video data. The driving voltage corresponding to the digital video data is thereby outputted to the source line.
During the remaining period excluding the normal operation period in one horizontal synchronizing period, the first switch is turned to OFF state in response to the first switching signal. A power supply to the resistance elements is thereby shut off, and an electric current constantly flowing in the resistance element becomes xe2x80x9c0xe2x80x9d. It is thereby made possible to reduce the electric power consumed in the resistance elements during the low power period. In addition, during this low power period, the electrical connection between the driver circuit and the capacitive load is cut off by the means for cutting off the electrical connection. The potential of the capacitive load is thereby retained, and it is made possible to prevent a deterioration of the display characteristics of the liquid crystal resulting from a potential variation of the pixel electrodes. As a result, it is made possible that an entire period excluding a period necessary to change the voltage of the capacitive load is made to be the low power period.
The term xe2x80x9cnormal operation periodxe2x80x9d herein is intended to mean, as defined in detail in xe2x80x9cthe Best Mode for Carrying Out the Inventionxe2x80x9d hereinafter, (1) a period during which a potential of a source line reaches a desired potential (i.e., a source line writing period) in the case where a gate pulse is provided to a pixel transistor after the potential of the source line completely reaches the desired voltage, or (2) a period during which a potential of a pixel electrode reaches a desired potential (i.e., a pixel electrode writing period) in the case where the time at which a gate pulse is provided to a pixel transistor and the time at which a potential of a source line begins to change by the change of an output voltage from a driver circuit are almost simultaneous. In other words, the term xe2x80x9cnormal operation periodxe2x80x9d means a period in which, with a various capacitances connected to a source line taken into consideration, a DAC must continue to output a driving voltage corresponding to a digital data so as to substantially completely change a potential of a pixel electrode. Therefore, in one horizontal synchronizing period, it is not necessary for a DAC to continue a normal operation during a remaining period in which the normal operation period is excluded. Hence, the present invention achieves an effect of reducing power consumption when compared with prior arts in which a DAC continues a normal operation during the remaining period as well as the normal operation period.
The xe2x80x9cmeans for cutting off the electrical connection between the driver circuit and a capacitive loadxe2x80x9d may be (1) a construction in which an output switch is provided on the output side in a driver circuit, and the switch is turned to ON state during the normal operation period and OFF state during the remaining period, or may be (2) a construction in which a driving power supply for the current amplifier element is turned to ON state during the normal operation period and OFF state during the remaining period. However, this construction (2) is limited for an amplifier element having a construction where an output impedance results in high impedance when the driving power supply is turned OFF. For an amplifier element with a construction where the output impedance does not results in high, an output switch should be provided. Further, it may be (3) a construction in which a group of second switches in the DAC is forcibly turned OFF during the remaining period.
In accordance with the 14th aspect of the invention, there is provided a driver circuit as in the 13th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction, the electrical connection between the driver circuit and the capacitive load connected to the source line is cut off during the remaining period by the output switch provided on the output side in the driver circuit. By contrast, according to a construction of cutting off the power supply of the amplifier, there arises some cases in which the output impedance does not become high when the power supply is cut off, depending on the construction of the amplifier element. In these cases, it is not possible to cut off the electrical connection between the driver circuit and the capacitive load. In addition, in a construction of turning OFF a group of second switches forcibly, the circuit design becomes slightly more complex since it is necessary to previously store a fixed data for cutting off the group of second switches and to provide a switch for selecting a video data during the normal operation period and the fixed data during the low power period. On the other hand, according to the above construction with the output switch, it is easily made possible to cut off the electrical connection with the capacitive load because the above-described difficulties do not occur.
In accordance with the 15th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC is composed of a voltage potentiometer type DAC comprising:
a series circuit wherein the resistance elements are connected in series, one end of the series circuit is commonly connected to a first high voltage power supply terminal and a second high voltage power supply terminal having a lower voltage level than the first high voltage power supply, and the other end is connected to a low voltage power supply terminal;
a third switch connected between one end of the series circuit and the power supply terminals, the third switch for switching an electrical connection of the one end of the series circuit in response to the first switching signal so that the one end of the series circuit is connected to the first high voltage power supply terminal during the normal operation period and is connected to the second high voltage power supply terminal during the remaining period; and
a group of second switches wherein a switching state of each of the second switches is controlled in response to a digital video data, and each of the second switches is connected between a connecting point of each of the resistance elements and an output terminal of the DAC.
According to the above construction, the following effects are attained.
During the normal operation period, the third switch is switched to the first high voltage power supply side in response to the first switching signal, and the switching states of the group of second switches are controlled in response to the digital video data. Thereby, a driving voltage corresponding to the digital video data is outputted to the source line.
During the remaining period, the third switch is switched to the second high voltage power supply side in response to the first switching signal. Thereby, the reduction in power consumption can be achieved by reducing the current flowing in the DAC. In addition, in the low power period, the electrical connection between the driver circuit and the capacitive load is cut off by the means for cutting off the electrical connection with the capacitive load. The potential of the capacitive load is thereby retained. Consequently, it is made possible that an entire period excluding a period necessary to change a voltage of the capacitive load is set to be the low power period.
According to this construction, it is possible to fix a potential in the circuit since a certain fixed current flows in the circuit, although the degree of the reduction in power consumption is slightly less than a construction with the means for cutting off the power supply. Therefore, it is made possible to reduce the occurrence of a signal noise resulting from a sudden current increase caused by a normal operation voltage at the transition to the normal operation period.
In accordance with the 16th aspect of the invention, there is provided a driver circuit as in the 15th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 17th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC is composed of an R-2R ladder type DAC comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of fourth switches, each provided for each bit of digital video data, for determining an output voltage by alternatively selecting between a connecting state with a high voltage power supply terminal and a connecting state with a low voltage power supply terminal; and
a second switching signal generator circuit for generating a second switching signal to control a switching state of each of the fourth switches and outputting the second switching signal to the group of fourth switches, wherein the second switching signal generator circuit receives the first switching signal and the digital video data, and outputs a data corresponding to the digital video input data as the second switching signal during the normal operation period, and outputs a fixed data as the second switching signal during the remaining period, the fixed data causing a current value in the resistance element network to be not more than an median current value between a minimum current value and a maximum current value in the resistance element network.
According to the above construction, the following effects are attained.
During the normal operation period, the second switching signal generator circuit outputs the second switching signal corresponding to the digital video input data. A driving voltage corresponding to the digital video input data is thereby outputted to the source line.
During the remaining period, the second switching signal generator circuit makes the input data into an fixed input data which results in a current value flowing in the resistance network being not more than the median current value between the minimum current value and the maximum current value, and outputs the fixed data as a second switching signal to the group of fourth switches. Thereby, the power consumption in the DAC is made less than the average power consumption in prior arts, in which a DAC continues the normal operation throughout one horizontal synchronizing period. As a result, this construction too achieves the reduction in power consumption of the DAC.
According to this construction, it is possible to fix a potential in the circuit since a certain fixed current flows in the circuit, although the degree of the reduction in power consumption is slightly less than a construction with the means for cutting off the power supply. Therefore, it is made possible to reduce the occurrence of a signal noise resulting from a sudden current increase caused by a normal operation voltage at the transition to the normal operation period.
In accordance with the 18th aspect of the invention, there is provided a driver circuit as in the 17th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 19th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC is composed of an R-2R ladder type DAC comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of fifth switches for determining an output voltage; and
a third switching signal generator circuit for generating a third switching signal to control a switching state of each of the fifth switches and outputting the third switching signal to the group of fifth switches, the third switching signal generator circuit comprising a storage circuit for storing a fixed data causing the group of fifth switches to be OFF state, wherein the third switching signal generator circuit receives the first switching signal and digital video data, and outputs during the normal operation period a data corresponding to the digital video data as the third switching signal, and outputs during the remaining period the fixed data stored in the storage circuit as the third switching signal so as to cut off the power supply to the resistance element network.
According to the above construction, the following effects are attained.
During the normal operation period, the third switching signal generator circuit outputs the third switching signal corresponding to the digital video input data. A driving voltage corresponding to the digital video input data is thereby outputted to the source line.
During the remaining period, the third switching signal generator circuit outputs the fixed data stored in the storage circuit as a third switching signal. All of the fifth switches are thereby turned to OFF state. Consequently, the current flowing in the circuit results in xe2x80x9c0xe2x80x9d, and the reduction in power consumption is thus attained.
In accordance with the 20th aspect of the invention, there is provided a driver circuit as in the 19th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 21st aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section, which comprises a first connecting terminal receiving a higher voltage output from the first DAC section and a second connecting terminal receiving a lower voltage output from the first DAC section, which employs as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and which operates in response to lesser significant bits of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is connected to a high voltage power supply terminal, and the other end is connected to a low voltage power supply terminal;
a sixth switch connected between one end of the series circuit and the high voltage power supply terminal or between the other end of the series circuit and the low voltage power supply circuit, the sixth switch to be turned to an ON state during the normal operation period and to be turned to an OFF state during the remaining period in response to the first switching signal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value; and
a group of ninth switches for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal in response to the lesser significant bits of the digital video input data;
the driver circuit, wherein:
during the normal operation period, the sixth switch is turned to the ON state, a switching state of each of the seventh switches and a switching state of each of the eighth switches are controlled corresponding to the more significant bits of the digital video input data, and a switching state of each of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the remaining period, the sixth switch is turned to the OFF state and the electrical connection with the capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, the following effects are attained.
During the normal operation period, the sixth switch is turned to ON state, the switching states of the seventh switches and eighth switches are controlled in response to the more significant bits of the digital video data, and the switching state of the ninth switch is controlled in response to the lesser significant bits of the digital video data. A driving voltage corresponding to the digital video input data is thereby outputted to the source line.
During the remaining period, the sixth switch is turned to OFF state, and in addition, the electrical connection between the driver circuit and the capacitive load is cut off by the aforementioned means for cutting off the electrical connection. The current flowing in the circuit thereby becomes xe2x80x9c0xe2x80x9d, and the reduction in power consumption is thus attained. In other words, the reduction in power consumption is achieved by cutting off the power supply of the first DAC section, the first DAC section being a voltage potentiometer type and allotted for the more significant bits.
In accordance with the 22nd aspect of the invention, there is provided a driver circuit as in the 21st aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 22nd aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section, which comprises a first connecting terminal receiving a higher voltage output from the first DAC section and a second connecting terminal receiving a lower voltage output from the first DAC section, which employs as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and which operates in response to lesser significant bits of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is commonly connected to a first high voltage power supply terminal and a second high voltage power supply terminal having a lower voltage level than the first high voltage power supply terminal via a tenth switch for selecting a power supply, the tenth switch controlled by the first switching signal, and the other end of the series circuit is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value; and
a group of ninth switches for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal in response to the lesser significant bits of the digital video input data;
the driver circuit wherein:
during the normal operation period, the tenth switch is switched to the first high voltage power supply terminal, a switching state of the seventh switches and a switching state of the eighth switches are controlled corresponding to the more significant bits of the digital video input data, and a switching state of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the remaining period, the tenth switch is switched to the second high voltage power supply terminal and the electrical connection with a capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, the following effects are attained.
During the normal operation period, the tenth switch for selecting the power supply is switched to the first high voltage power supply terminal side, the switching states of the seventh switches and eighth switches are controlled in response to the more significant bits of the digital video data, and the switching state of the ninth switch is controlled in response to the lesser significant bits of the digital video data. A driving voltage corresponding to the digital video data is thereby outputted to the source line.
During the remaining period, the tenth switch for selecting the power supply is switched to the second high voltage power supply terminal side, and the electrical connection with the capacitive load is cut off by the aforementioned means for cutting off the electrical connection. The current flowing in the circuit is thereby reduced, and the reduction in power consumption is thus attained. In other words, the reduction in power consumption is achieved by selecting a power supply voltage of the first DAC section, the first DAC section being a voltage potentiometer type and allotted for the more significant bits.
In accordance with the 24th aspect of the invention, there is provided a driver circuit as in the 23rd aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 25th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section, which comprises a first connecting terminal receiving a higher voltage output from the first DAC section and a second connecting terminal receiving a lower voltage output from the first DAC section, which employs as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and which operates in response to lesser significant bits of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is connected to a high voltage power supply terminal, and the other end is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of ninth switches provided for each of the lesser significant bits of the digital input data for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal; and
a fourth switching signal generator circuit for generating a fourth switching signal to control a switching state of each of the ninth switches and outputting the fourth switching signal to the group of ninth switches, wherein the fourth switching signal generator circuit receives the lesser significant bits of the digital video input data and the first switching signal, and outputs during the normal operation period the fourth switching signal corresponding to the lesser significant bits of the digital video data, and outputs during the remaining period a fixed data as the fourth switching signal, the fixed data causing a current value in the resistance element network to be not more than the median current value between a minimum current value and a maximum current value in the resistance element network.
According to the above construction, the following effects are attained.
During the normal operation period, the switching state of the seventh and eighth switches are controlled in response to the more significant bits, and the ninth switches are switched to either a high voltage power supply or a low voltage power supply so as to obtain a driving voltage corresponding to the video data. The driving voltage corresponding to the digital video input data is thereby outputted to the source line.
During the remaining period, the fourth switching signal generator circuit makes the input data into an fixed input data which results in a current value in the resistance network being not more than the median current value between the minimum current value and the maximum current value, and outputs the fixed data as the fourth switching signal to the group of ninth switches. The power consumption in the second DAC section is thereby reduced, and the reduction in power consumption is thus attained. In other words, the reduction in power consumption is achieved by selecting an input data to the second DAC section, the second DAC section being an R-2R ladder type and allotted for the lesser significant bits.
In accordance with the 26th aspect of the invention, there is provided a driver circuit as in the 25th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 27th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section comprising a first connecting terminal receiving a higher voltage output from the first DAC section, an eleventh switch connected between the first connecting terminal and a power supply input line connected to the first connecting terminal, a second connecting terminal receiving a lower voltage output from the first DAC section, and a twelfth switch connected between the second connecting terminal and a power supply input line connected to the second connecting terminal, the second DAC section employing as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and the second digital-to-analog converter operating in response to lesser significant bit of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is connected to a high voltage power supply terminal, and the other end is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section further comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value; and
a group of ninth switches provided for each of the lesser significant bits of the digital input data for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal;
the driver circuit wherein:
during the normal operation period, the eleventh switch and the twelfth switch are turned to an ON state and a switching state of each of the seventh switches and a switching state of each of the eighth switches are controlled corresponding to the more significant bits of the digital video input data, and a switching state of each of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the remaining period, the eleventh switch and the twelfth switch are turned to the OFF state and the electrical connection with the capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, the following effects are attained.
During the normal operation period, the eleventh switch and twelfth switch is turned to ON state, the switching state of the seventh and eighth switches are controlled in response to the more significant bits of the digital video data, and the switching states of the ninth switches are controlled in response to the lesser significant bits of the digital video data. A driving voltage corresponding to the digital video input data is thereby outputted to the source line.
During the remaining period, the eleventh switch and twelfth switch is turned to OFF state. The current flowing in the second DAC section becomes xe2x80x9c0xe2x80x9d, and the reduction in power consumption is thus attained. In other words, the reduction in power consumption is achieved by cutting off the power supply of the second DAC section, the second DAC section being an R-2R ladder type and allotted for the lesser significant bits.
In accordance with the 28th aspect of the invention, there is provided a driver circuit as in the 27th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 29th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section, which comprises a first connecting terminal receiving a higher voltage output from the first DAC section and a second connecting terminal receiving a lower voltage output from the first DAC section, which employs as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and which operates in response to lesser significant bits of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is commonly connected to a first high voltage power supply terminal and a second high voltage power supply terminal having a lower voltage level than the first high voltage power supply terminal via a tenth switch for selecting a power supply, and the other end of the series circuit is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of ninth switches provided for each of the lesser significant bits of the digital input data for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal; and
a fourth switching signal generator circuit for generating a fourth switching signal to control a switching state of each of the ninth switches and outputting the fourth switching signal to the group of ninth switches, wherein the fourth switching signal generator circuit receives the lesser significant bits of the digital video input data and the first switching signal, and outputs during the normal operation period the fourth switching signal corresponding to the lesser significant bits of the digital video data, and outputs during the remaining period a fixed data as the fourth switching signal, the fixed data causing a current value in the resistance element network to be not more than the median current value between a minimum current value and a maximum current value in the resistance element network;
the driver circuit wherein:
during the normal operation period, the tenth switch is switched to the first high voltage power supply terminal, a switching state of the seventh switches and a switching state of the eighth switches are controlled corresponding to the more significant bits of the digital video input data, and a switching state of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the remaining period, the tenth switch is switched to the second high voltage power supply terminal, the ninth switches are switched corresponding to the fixed input data, and the electrical connection with the capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, the following effects are attained.
During the normal operation period, the tenth switch for selecting the power supply is switched to the first high voltage power supply terminal side, the switching states of the seventh switches and eighth switches are controlled in response to the more significant bits of the digital video data, and the ninth switches are switched to either a high voltage side or a low voltage side so as to obtain a driving voltage corresponding to the lesser significant bits of the video data. The driving voltage corresponding to the digital video data is thereby outputted to the source line.
During the remaining period, the tenth switch for selecting the power supply is switched to the second high voltage power supply terminal side, the ninth switches are switched in response to the aforementioned fixed input data, and the electrical connection with the capacitive load is cut off by the aforementioned means for cutting off the electrical connection. The second high voltage power supply is selected in the first DAC section, and the current flowing in the circuit is thereby reduced, and the supplied power for the second DAC section is accordingly reduced. In addition, in the second DAC section, the power consumption is further reduced with the use of the fixed data. In other words, the reduction in power consumption is achieved by selecting the power supply voltages of the first DAC section, the first DAC section being a voltage potentiometer type and allotted for the more significant bits, as well as by selecting the input data to the second DAC section, the second DAC section being an R-2R ladder type and allotted for the lesser significant bits.
In accordance with the 30th aspect of the invention, there is provided a driver circuit as in the 29th aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 30th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a first switching signal generator circuit which receives a predetermined reference signal and generates a first switching signal for alternatively selecting between a normal operation period and a remaining period; and
means for cutting off an electrical connection between the driver circuit and a capacitive load connected to a source line only during the remaining period in response to the first switching signal;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section comprising a first connecting terminal receiving a higher voltage output from the first DAC section, an eleventh switch connected between the first connecting terminal and a power supply input line connected to the first connecting terminal, a second connecting terminal receiving a lower voltage output from the first DAC section, and a twelfth switch connected between the second connecting terminal and a power supply input line connected to the second connecting terminal, the second DAC section employing as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and the second digital-to-analog converter operating in response to lesser significant bit of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is commonly connected to a first high voltage power supply terminal and a second high voltage power supply terminal having a lower voltage level than the first high voltage power supply terminal via a tenth switch for selecting a power supply, and the other end of the series circuit is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value; and
a group of ninth switches provided for each of the lesser significant bits of the digital input data for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal;
the driver circuit wherein:
during the normal operation period, the tenth switch is switched to the first high voltage power supply terminal, a switching state of the seventh switches and a switching state of the eighth switches are controlled corresponding to the more significant bits of the digital video input data and a switching state of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the remaining period, the tenth switch is switched to the second high voltage power supply terminal, the eleventh switch and the twelfth switch are turned to the OFF state and the electrical connection with the capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, the following effects are attained.
During the normal operation period, the tenth switch for selecting the power supply is switched to the first high voltage power supply terminal side, the switching states of the seventh switches and eighth switches are controlled in response to the more significant bits of the digital video data, the ninth switches are switched to either a high voltage side or a low voltage side so as to obtain a driving voltage corresponding to the lesser significant bits of the video data, and the eleventh switch and twelfth switch are turned to ON state. A driving voltage corresponding to the digital video data is thereby outputted to the source line.
During the remaining period, the tenth switch for selecting the power supply is switched to the second high voltage power supply terminal side, the eleventh switch and twelfth switch are turned to OFF state, and the electrical connection with the capacitive load connected to the source line is cut off by the aforementioned means for cutting off the electrical connection. The second high voltage power supply is selected for the first DAC section, and the current flowing in the circuit is thereby reduced. In the second DAC section, the current flowing in the circuit becomes xe2x80x9c0xe2x80x9d by the cutting off the power supply. In other words, the reduction in power consumption is achieved by selecting the power supply voltages of the first DAC section, the first DAC section being a voltage potentiometer type and allotted for the more significant bits, as well as by cutting off the power supply to the second DAC section, the second DAC section being an R-2R ladder type and allotted for the lesser significant bits.
In accordance with the 32nd aspect of the invention, there is provided a driver circuit as in the 31st aspect of the invention, wherein the means for cutting off the electrical connection between the driver circuit and the capacitive load connected to the source line is such an output switch provided on an output side of the driver circuit that, in response to the first switching signal, the output switch is turned to an ON state during the normal operation period, and is turned to an OFF state during the remaining period so as to cut off the electrical connection.
According to the above construction employing the output switch, it is made possible to completely cut off the electrical connection with the capacitive load by a simple circuit construction.
In accordance with the 33rd aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a fifth switching signal generator circuit which receives a predetermined reference signal and generates a fifth switching signal for selecting one of the modes between a precharge period mode for a precharge which is carried out prior to writing video data into a source line and a remaining period mode excluding the precharge period mode;
wherein the DAC is composed of an R-2R ladder type DAC comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of fourth switches, each provided for each bit of digital video data, for determining an output voltage by alternatively selecting between a connecting state with a high voltage power supply terminal and a connecting state with a low voltage power supply terminal; and
a sixth switching signal generator circuit for generating a sixth switching signal to control a switching state of each of the fourth switches and outputting the sixth switching signal to the group of fourth switches, wherein the sixth switching signal generator circuit receives the fifth switching signal and digital video data, and outputs a data corresponding to the digital video data as the sixth switching signal during the remaining period, and outputs a fixed data as the sixth switching signal during the precharge period, the fixed data causing a current value in the resistance element network to be not more than an median current value between a minimum current value and a maximum current value in the resistance element network.
According to the above construction, during the precharge period, a combination of the switching states of the fourth switches is made, by the sixth switching signal generator circuit, to be such a combination as results in a current value in the resistance network being not more than the median current value between the minimum current value and the maximum current value in the resistance network. Therefore, it is made possible to reduce the power consumption in the precharge period.
In accordance with the 34th aspect of the invention, there is provided a driver circuit as in one of the first to third aspects of the invention, further comprising:
a fifth switching signal generator circuit which receives a predetermined reference signal and generates a fifth switching signal for selecting one of the modes between a precharge period mode for a precharge which is carried out prior to writing video data into a source line and a remaining period mode excluding the precharge period mode;
wherein the DAC comprises:
a first DAC section which operates in response to more significant bits of digital video input data; and
a second DAC section, which comprises a first connecting terminal receiving a higher voltage output from the first DAC section and a second connecting terminal receiving a lower voltage output from the first DAC section, which employs as a reference voltage a voltage between the first connecting terminal and the second connecting terminal, and which operates in response to lesser significant bits of the digital video input data;
the first DAC section being composed of a voltage potentiometer type DAC and the second DAC section being composed of an R-2R ladder type DAC;
the first DAC section comprising:
a series circuit wherein a plurality of the resistance elements are connected in series, one end of the series circuit is commonly connected to a first high voltage power supply terminal and a second high voltage power supply terminal having a lower voltage level than the first high voltage power supply terminal via a tenth switch for selecting a power supply, and the other end of the series circuit is connected to a low voltage power supply terminal;
a group of seventh switches each connected between a connecting point of each of the resistance elements in the series circuit and the first connecting terminal, the seventh switches controlled by the more significant bits of the digital video input data; and
a group of eighth switches each connected between a connecting point of each of the resistance elements in the series circuit and the second connecting terminal, the eighth switches controlled by the more significant bits of the digital video input data;
the second DAC section comprising:
an R-2R ladder resistance element network composed of two types of the resistance elements, each type having a different resistance value;
a group of ninth switches provided for each of the lesser significant bits of the digital input data for alternatively selecting between a connecting state with the first connecting terminal and a connecting state with the second connecting terminal; and
a fourth switching signal generator circuit for generating a seventh switching signal to control a switching state of each of the ninth switches and outputting the seventh switching signal to the group of ninth switches, wherein the seventh switching signal generator circuit receives the fifth switching signal and the lesser significant bits of the digital video data, and outputs a data corresponding to the lesser significant bits of the digital video input data as the seventh switching signal during the remaining period, and outputs a fixed data as the seventh switching signal during the precharge period, the fixed data causing a current value in the resistance element network to be not more than an median current value between a minimum current value and a maximum current value in the resistance element network;
the driver circuit wherein:
during the remaining period, the tenth switch is switched to the first high voltage power supply terminal, a switching state of the seventh switches and a switching state of the eighth switches are controlled corresponding to the more significant bits of the digital video input data, and a switching state of the ninth switches is controlled corresponding to the lesser significant bits of the digital video input data; and
during the precharge period, the tenth switch is switched to the second high voltage power supply terminal, the ninth switches are switched corresponding to the fixed input data, and the electrical connection with the capacitive load is cut off by the means for cutting off the electrical connection.
According to the above construction, during the remaining period excluding the precharge period, the tenth switch for selecting the power supply is switched to the first high voltage power supply terminal side, the switching states of the seventh switches and eighth switches are controlled corresponding to the more significant bits of the digital video data, and the ninth switches are switched to either a high power supply or low power supply so as to obtain a driving voltage corresponding to the lesser significant bits of the video data.
During the precharge period, the tenth switch for selecting the power supply is switched to the second high voltage power supply terminal side, and the ninth switches are switched in response to the aforementioned fixed data. It is thereby made possible to reduce the power consumption in the precharge period.
In accordance with the 35th aspect of the invention, there is provided a driver circuit as in the 13th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the first switching signal is generated by which an output signal from the delay circuit for delaying the horizontal synchronizing signal for a predetermined time determined by a resistance value of the resistance element which composes the integrator circuit and a horizontal synchronizing signal are ANDed together, and therefore it is made possible to determine the length of a high level period of the first switching signal by the resistance value. Consequently, it is made possible to absorb the difference in the steady-state currents flowing in the resistance elements in the DAC, which is caused by a variation of the resistance values of the resistance elements in each substrate.
The description below further details the above effect. In the case of a resistance element on an array substrate having a high resistance value, it is preferable that the low power period be short, since the current flowing in the DAC is relatively small and therefore it takes relatively a long time to charge a capacitive load connected to a source line SL. In this case, even if the low power period is made short (i.e., the normal operation period is made long), no adverse effect occurs in view of the reduction in power consumption because the power consumption during the normal operation period is decreased by the resistance elements having a high resistance value. On the other hand, in the case of a resistance element having a low resistance value, it is preferable that the low power period be long, since the current flowing in the DAC is relatively large and therefore the time required for charging the source line becomes relatively short. When there arises a need to change the lengths of the normal operation period and the low power period according to the resistance values of the resistance elements on each of the array substrates in order to meet the two requirements, one being the charging of the source line and the other being the reduction in power consumption, this construction enables the length of the high level period of the first switching signal to be automatically adjusted to the most suitable length by the first switching signal generator circuit so that it can meet the two requirements. It is therefore made possible to automatically carry out an adjustment for optimizing the power consumption regardless of the precision of the resistance elements, by constructing the integrator circuit with the resistance element formed on the same array substrate as the one on which the resistance elements of the DAC are formed. As a result, it is made possible to automatically carry out the adjustment for optimizing the power consumption for all the substrates regardless of the variation of the resistance elements.
In accordance with the 36th aspect of the invention, there is provided a driver circuit as in the 15th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 37th aspect of the invention, there is provided a driver circuit as in the 17th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 38th aspect of the invention, there is provided a driver circuit as in the 19th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 39th aspect of the invention, there is provided a driver circuit as in the 21st aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 40th aspect of the invention, there is provided a driver circuit as in the 23rd aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 41st aspect of the invention, there is provided a driver circuit as in the 25th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 42nd aspect of the invention, there is provided a driver circuit as in the 27th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 43rd aspect of the invention, there is provided a driver circuit as in the 29th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 44th aspect of the invention, there is provided a driver circuit as in the 31st aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitor element, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 35th aspect of the invention can be attained.
In accordance with the 45th aspect of the invention, there is provided a driver circuit as in the 13th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the optimization of the normal operation period can be realized with taking into consideration not only a variation of the resistance element but also a variation of the capacitive load by employing the capacitive load connected to the source line as the capacitance element in the integrator circuit.
In accordance with the 46th aspect of the invention, there is provided a driver circuit as in the 15th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 47th aspect of the invention, there is provided a driver circuit as in the 17th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 48th aspect of the invention, there is provided a driver circuit as in the 19th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 49th aspect of the invention, there is provided a driver circuit as in the 21st aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 50th aspect of the invention, there is provided a driver circuit as in the 23rd aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 51st aspect of the invention, there is provided a driver circuit as in the 25th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 52nd aspect of the invention, there is provided a driver circuit as in the 27th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 53rd aspect of the invention, there is provided a driver circuit as in the 29th aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.
In accordance with the 54th aspect of the invention, there is provided a driver circuit as in the 31st aspect of the invention, wherein the first switching signal generator circuit receives a horizontal synchronizing signal, generates a first switching signal from the horizontal synchronizing signal, and outputs the first switching signal to the DAC:
the first switching signal generator circuit comprising:
a delay circuit comprising an integrator circuit composed of a resistance element and a capacitance element composed of a capacitive load connected to a source line, the delay circuit for delaying the horizontal synchronizing signal for a predetermined delay time determined by a resistance value of the resistance element in the integrator circuit and a capacitance value of the capacitance element in the integrator circuit; and
a logic circuit wherein an output from the delay circuit and the horizontal synchronizing signal are ANDed together to output a resultant signal as the first switching signal.
According to the above construction, the same effect as in the 45th aspect of the invention can be attained.